Red Pitaya Engineering Kit SDRlab

The Red Pitaya SDRlab 122-16 External clock Starter kit version is standard STEMlab 122-16 modified in such a way that the ADC and DAC clock can be provided from an external source clock. External clock should be connected to Ext ADC CLK- and + pins. External clock signal levels should be LVDS in the range from 1 MHz to 122.8 MHz according to ADC spec.

• Dual-Core ARM Cortex-A9 MPCore processor
• 512MB (4Gb) RAM
• Tailored for SDR & other RF applications, HF and 50MHz bands
• Comes with two 16 bit ADCs 50 ohm inputs; 14 bit DACs 50 ohm outputs
• Three times bigger dual core ARM Cortex A9 + Xilinx Zynq 7020 FPGA
• Bigger FPGA provides more real-time processing capabilities
• Hardware compatible with HPSDR
• Improved distortions, dynamic range, sensitivity, noise & crosstalk